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Understanding the Energy Consumption of Dynamic Random Access Memories
Energy consumption has become a major constraint on the capabilities of computer systems. In large systems the energy consumed by Dynamic Random Access Memories (DRAM) is a significant part of the total energy consumption. It is possible...
Understanding the Energy Consumption of Dynamic Random Access Memories

A 5Gb/s Link with Clock Edge Matching and Embedded Common Mode Clock for ...
A 5Gb/s signaling system was designed and fabricated in TSMC’s 40nm LP CMOS process. A new clock/data skew minimization technique with a source-synchronous transmit clock delay line and integrating receiver tolerates high frequency ...
A 5Gb/s Link with Clock Edge Matching and Embedded Common Mode Clock for ...

Overcoming the Full Well Capacity Limit: High Dynamic Range Imaging Using ...
We describe a high dynamic range image sensor that oversamples the incident light in time by using the ADC output at each sampling as part of the final response and resetting the pixel only if a threshold has been exceeded. We show that ...
Overcoming the Full Well Capacity Limit: High Dynamic Range Imaging Using ...

Challenges and Solutions for Future Main Memory
DDR3 SDRAM is being used in many computing systems today and offers data rates of up to 1600Mbps. To achieve performance levels beyond DDR3, future main memory subsystems must attain faster data rates while maintaining low power, access ...
Challenges and Solutions for Future Main Memory

Accurate System Voltage and Timing Margin Simulation in High-Speed I/O ...
This paper appears in the November 2008 issue of "IEEE Transactions on Advanced Packaging" and is available for purchase on the IEEE website.
Accurate System Voltage and Timing Margin Simulation in High-Speed I/O ...

FPGA to IBM Power Processor Interface Setup
Rambus collaborated with IBM and Xilinx to establish a high-bandwidth interface between an IBM Power Processor and the latest Xilinx FPGAs via Rambus' FlexIO™ processor bus interface. Read this application note to learn more.
FPGA to IBM Power Processor Interface Setup

Signal and Power Integrity for a 1600 Mbps DDR3 PHY in Wirebond Package
A DDR3 interface for a data rate of 1600MHz using a wirebond package and a low-cost system environment typical for consumer electronics products was implemented. In this environment crosstalk and supply noise are serious challenges and ...
Signal and Power Integrity for a 1600 Mbps DDR3 PHY in Wirebond Package

A Way to Meet Bandwidth and Capacity Needs of Next Generation Main Memory
Signal integrity issues pose a challenge to increasing the data rates of single ended systems. This paper presents techniques that help in increasing the data rates of next generation main memory systems to 1600-3200 Mbps range without ...
A Way to Meet Bandwidth and Capacity Needs of Next Generation Main Memory

High Performance, Low Cost DDR3- 1600Mbps+ Consumer Electronics Memory ...
Paper presents a co-design approach for low cost, high performance consumer DDR3 memory interface. Design considerations are analyzed at every hierarchy (silicon/package/PCB) to meet performance and cost constraints. Strategies for cross...
High Performance, Low Cost DDR3- 1600Mbps+ Consumer Electronics Memory ...

Modeling and Simulation of Common Clocking Topologies for Statistical Link
Statistical link analysis has gained significant importance as high-speed interconnect designs require accurate bit error rate prediction with device jitter and noise. Currently available statistical analysis techniques focus on modeling...
Modeling and Simulation of Common Clocking Topologies for Statistical Link

Practical Design Considerations for 10 to 25 Gbps Copper Backplane Serial Links
There is a general consensus that 10 Gbps copper backplane serial links will be deployed in the near future. This paper takes a look at the practical and cost effective design aspects of the 10-12.5 Gbps links as well as the feasibility ...
Practical Design Considerations for 10 to 25 Gbps Copper Backplane Serial Links

Study of Signal and Power Integrity Challenges in High-Speed Memory I/O ...
In contrast to most chip-to-chip I/O interfaces that use differential signaling, the mainstream memory interface designs are based on single-ended signaling such as SSTL or PODL. Extending the data rate for single-ended signaling beyond ...
Study of Signal and Power Integrity Challenges in High-Speed Memory I/O ...

Analyzing the Impact of Simultaneous Switching Noise on System Margin in ...
Simultaneous switching noise is a major performance limiter for single-ended signaling systems as data rates scale higher. This paper presents a methodology to analyze the performance of single-ended interface systems like GDDR3 in the ...
Analyzing the Impact of Simultaneous Switching Noise on System Margin in ...

A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS
This paper describes a 6.25-Gb/s 14-mW transceiver in 90-nm CMOS for chip-to-chip applications. The transceiver employs a number of features for reducing power consumption, including a shared LC-PLL clock multiplier, an inductor-loaded ...
A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS

A Study of Optimal Data Rates of High-Speed Channels
The study of the optimal data rates of high-speed channel is presented. Based on the signaling power equations and the channel frequency response, the optimum signaling rate of a high-speed interconnect system is derived as a function of...
A Study of Optimal Data Rates of High-Speed Channels

On-Chip Characterization of Signal and Power Integrity in 3-D Packaged Systems
Characterization of I/O channels, signal quality, and supply noise in 3-D packaged systems is very challenging due to the small footprint and complex 3-D interaction. This paper presents several enabling techniques to allow on-chip ...
On-Chip Characterization of Signal and Power Integrity in 3-D Packaged Systems