Refinements

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Understanding the Energy Consumption of Dynamic Random Access Memories
Energy consumption has become a major constraint on the capabilities of computer systems. In large systems the energy consumed by Dynamic Random Access Memories (DRAM) is a significant part of the total energy consumption. It is possible...
Understanding the Energy Consumption of Dynamic Random Access Memories

The Next Generation of Mobile Memory
Visit Denali's website to hear Judy Chen's MemCon 2008 presentation, The Next Generation of Mobile Memory.
The Next Generation of Mobile Memory

Memory System Challenges in the Multi-Core Era
Visit Denali's website to hear Stephen Woo's MemCon 2008 presentation, Memory System Challenges in the Multi-Core Era.
Memory System Challenges in the Multi-Core Era

Memory Technology Innovations for Mobile Platforms
Visit Denali's website to hear Fred Ware's MemCon 2009 presentation, Memory Technology Innovations for Mobile Platforms.
Memory Technology Innovations for Mobile Platforms

Market Trends Shaping the Memory Industry
Rising design costs and complexity, shorter design cycles, and rapidly evolving system needs are shaping the semiconductor and memory markets. Responding to these challenges will require extending the current memory roadmap as well as...
Market Trends Shaping the Memory Industry

Beyond DDR3: Advancing the Main Memory Roadmap
Visit Denali's website to hear Michael Ching's MemCon 2009 presentation, Beyond DDR3: Advancing the Main Memory Roadmap.
Beyond DDR3: Advancing the Main Memory Roadmap

High-Speed I/O Interface Supply Noise and Reliability Analysis
Presented in the Apache booth at DAC 2009 by Rambus engineers, Ralf Schmitt and Hai Lan, this presentation covers Power Integrity analysis strategy that allows us to analyze supply quality for large mixed-signal interface systems with...
High-Speed I/O Interface Supply Noise and Reliability Analysis

Challenges and Solutions for GHz DDR3 Memory Interface Design
Visit Denali's website to hear Arun Vaidyanath's MemCon 2010 presentation, Challenges and Solutions for GHz DDR3 Memory Interface Design.
Challenges and Solutions for GHz DDR3 Memory Interface Design

Memory Architectures for Multi-Core Computing
See slides from Rambus Fellow Craig Hampel's presentation at the 2010 Multicore Expo. In this presentation, Mr. Hampel addresses memory architecture optimizations that can support the many threads and workloads handled by multi-core...
Memory Architectures for Multi-Core Computing

3D Si Interposer Design and Electrical Performance Study
Design guidelines for signal routing and signal integrity (loss, impedance control, crosstalk, eye diagram, etc.) for frequencies up to 20 GHz. Power delivery guidelines are presented for RDL layers, taking into consideration the IR...
3D Si Interposer Design and Electrical Performance Study

Meeting the Challenges for Next-Generation Mobile and Graphics Memory ...
Next-gen mobile and graphics systems share the need for higher-performance power-efficient memories to deliver compelling consumer experiences. With complexity rising dramatically as data rates increase, managing signal and power ...
Meeting the Challenges for Next-Generation Mobile and Graphics Memory ...

Trends in Consumer Electronics
Presented at Rambus Design Seminar Osaka 2009, this presentation discusses market developments in consumer electronics and how Rambus innovations enhance the end-user experience by increasing performance, reducing power, and lowering costs.
Trends in Consumer Electronics

Elpida DRAM Solutions to Advanced Digital Consumer Electronic Systems
Presented by Elpida at Rambus Design Seminar Osaka 2009, this presentation explores the requirements of next-generation digital consumer electronics, compares high-specification DRAM including Mobile RAM, DDR2, DDR3 and XDR, and proposes...
Elpida DRAM Solutions to Advanced Digital Consumer Electronic Systems

Impact of Backplane Connector Pin Field on Trace Impedance and Crosstalk
The signal integrity effects of lowered impedance and induced crosstalk are well understood when signals traverse through the PTH vias. However, the signal integrity impact on trace impedance and crosstalk in the vertical direction ...
Impact of Backplane Connector Pin Field on Trace Impedance and Crosstalk

Creating a Generic Behavioral Model – DDR based memory system using SystemC/TLM
In a typical design cycle, the behavioral models represent an executable architecture to be used for architectual explorations and performance analysis, as well as in customer simulations. They are required to stay ahead of RTL with ...
Creating a Generic Behavioral Model – DDR based memory system using SystemC/TLM

Performance Comparison of Edge-based Equalization and Data-based ...
To achieve high data rates over backplane channels, sophisticated equalization techniques must be used. Conventional data-based equalization techniques focus on reducing ISI at the eye center. Recently, edge-based equalization ...
Performance Comparison of Edge-based Equalization and Data-based ...